The present invention relates to delay-locked loop (DLL) circuits and phase-locked loop (PLL) circuits for use in, for example, programmable logic devices (PLDs). More particularly, this invention relates to DLL and PLL circuit phase comparators that include a low-pass noise filter with programmable bandwidth.
In general, a PLD is a general-purpose integrated circuit device that is programmable to perform any of a wide range of logic tasks. Instead of having to design and build separate logic circuits for performing different logic tasks, general-purpose PLDs can be programmed in various different ways to perform those different logic tasks. Many manufacturers of electronic circuitry and systems find the use of PLDs to be an advantageous way to provide various components of what they need to produce.
It is known to accommodate various input/output standards, some of which require very accurate internal clock signals, by incorporating DLL or PLL circuits on PLDs. For example, PLL and DLL circuits, collectively referred to herein as “loop circuits,” are often used in PLDs in clock distribution circuits, multiphase clock generation and clock recovery circuits. In particular, loop circuits may be used to provide an internal clock signal that tracks an external, or reference, clock signal (which may come from the output of an oscillator, a different loop circuit or another suitable source). For example, a loop circuit may be used to produce an internal clock signal that is synchronized with a reference clock signal and then distributed to different regions of the PLD.
On the other hand, a loop circuit (generally, a DLL circuit) may also be used to compensate for clock skew that often occurs in a PLD (or a system) when a centralized clock signal is being distributed to many different components in the PLD. In this case, the loop circuit is used to eliminate excessive delay in the propagating clock signals by providing an internal clock signal that is advanced in time relative to the reference clock signal (rather than synchronized with the reference clock signal). The advanced internal clock signal is propagated to portions of the PLD that are relatively distant from the applied reference clock signal so that the propagation delay brings the internal clock signal back into synchronization with the reference clock signal when it reaches the distant portions of the PLD. In this manner, all portions of the PLD receive substantially synchronous clock signals.
A basic digital DLL circuit includes, for example, a controlled delay line (or delay chain), a phase comparator and a delay setting counter. The controlled delay line receives a reference clock signal, and, in response to the delay setting counter, generates an internal clock signal.
In operation, the reference clock signal is one input to the phase comparator of a DLL circuit. A feedback signal derived from the output of the controlled delay line (which is also the output of the DLL circuit) is fed back to another input of the phase comparator, where the feedback signal is either the same as, or when clock skew is being accounted for, a delayed version of the controlled delay line output. On the basis of a detected phase difference between the reference clock signal and the feedback signal, the phase comparator adjusts the delay setting counter according to whether the feedback signal leads or lags the reference clock signal. Depending on whether the delay setting counter is incremented or decremented, the delay introduced by the controlled delay line is either increased or decreased, respectively. Eventually, the phase of the internal clock signal will track the phase of the reference clock signal.
The situation is similar for PLL circuits. Instead of using a controlled delay line, however, PLL circuits operate through the use of a controlled oscillator that produces a locally generated clock signal (i.e., an internal clock signal) having a frequency equal to the frequency of a reference clock signal. Moreover, because DLL circuits are not concerned with frequency, PLL circuits are typically used when frequency synthesis is required.
Initially, in a PLL circuit, the oscillator is tuned to a frequency close to the frequency of the reference clock signal. At this time, any slight change in phase between the frequency of the reference clock signal first appears as a change in phase between the reference clock signal and the internal clock signal produced by the controlled oscillator. This phase shift, as detected by the phase comparator, acts as an error signal to change the frequency of the oscillator to match the frequency of the reference clock signal. Accordingly, based on readings from the phase comparator, the oscillator is constantly adjusted to match in phase the frequency of the reference clock signal. In this manner, the controlled oscillator provides a clean replica of the reference clock signal frequency.
One consideration when using loop circuits is the fact that their performance is often degraded by the presence of noise. For example, noise coming directly from the reference clock signal, from the power supply or from another component may result in an erroneously detected phase difference between the reference clock signal and the feedback signal. When this happens, the internal clock signal generated by the loop circuit may not accurately track the reference clock signal because the controlled delay line in the DLL circuit or the controlled oscillator in the PLL circuit responds to this erroneous comparison. Moreover, while it is known to use filters in loop circuits, such filters are often detrimentally large and are not suitable for handling noises from varying sources which may have different noise spectral densities.